Multi-core processors may contain multiple processor cores which are connected to an on-die shared cache though a shared cache scheduler and coherence controller. Multi-core multi-processor systems are becoming increasingly popular in commercial server systems because of their improved scalability and modular design. The coherence controller and the shared cache can either be centralized or distributed among the cores depending on the number of cores in the processor design. The shared cache is often designed as an inclusive cache to provide good snoop filtering. Cross-snoop transactions may be used to provide efficient sharing of the on-die cache between multiple cores. However, writeback transactions from the core caches need to update the shared cache to maintain its inclusive nature. These in-flight core writebacks and cross-snoop transactions can conflict with each other in multiple time windows.
In addition to recovery from writeback and cross-snoop transaction conflicts, within a multi-core processor a caching bridge may be used. The caching bridge may be the scheduling logic that handles all incoming and outgoing transactions from the cores and the system interconnect. Incoming snoop transactions may arrive at this package on the system interconnect. There a queue structure that handles all incoming snoop transactions, called a snoop queue, may be used. Snoop transactions are expected to be frequent in server applications as more threads are sharing the same address space. For this reason, any improved use of the snoop path may result in an overall system performance increase.